Study note of LabVIEW FPGA (1)

Tuesday, July 20th, 2010

Currently I’m studying FPGA module of LabVIEW. It is  quite a different task from my previous project. Before this, I was using M series DAQ card with DAQmx. I’m not even sure why I have to use FPGA of this project.

So now I *figure out* the reason might be:
The latency is known on FPGA; there is no OS on the H/W, which means a more robust system; there are more I/O ports for data acquisition; if we take use of the parallel algrithm properly, we might achieve a faster system; FPGA sounds cool.

As I said, the way of programming FPGA is different. It looks like you are using global variable through your target vi (code on the FPGA) and host vi (code on the computer). And you use sequence structure instead of data flow to force the execution order. Error cluster is not recommended, which costs *memory*. Some of my *good* programming habits have to be abandoned when I program on the target vi.

So, what I mastered so far is only to create a project generating digital output on lines or ports. I can either put the ‘calculation’ on the target or on the host. I think the questions need to thought of using FPGA are: Does it need UI? Does is cost lots of memory? Is there any calculation very complex that only can be implemented on the computer?  If all the answers are NO, we can put it on the target, or else we have to use the host pc to do the calculation.

My next move is trying to generate a clock together the signal. The rising edge of the clock shold be within signal pulses. This is very useful when we drive the SLM in the future.

Related Posts: Study note of LabVIEW FPGA (2) ,
Study note of LabVIEW FPGA (3) — Multi-line transmission


2 comments on “Study note of LabVIEW FPGA (1)

  1. […] Posts: Study note of LabVIEW FPGA (1)                           Study note of LabVIEW FPGA (3) — […]

  2. […] Posts: Study note of LabVIEW FPGA (1)                           Study note of LabVIEW […]

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