Study note of LabVIEW FPGA (2)

Wednesday, July 28th, 2010

After a few days of using LabVIEW FPGA, here are some thoughts:
It IS much more convinient programming in LabVIEW. When I came up with some problems, I spent very few time checking the logic rather than considering the syntax (which is fine) and the logic cycle (which is a nightmare);
The conversion of bitstream file takes longer and longer. At first it takes about 6 minutes, a length for pee, as the code grows now it takes about 20 minutes, a time for lunch. I can’t imagine how long it would take when I do a more complex work;
The genenration of clock and signals works:)
We can use Target-Scoped FIFO to perform a Producer-Consumer Loop in FPGA vi;
The size of the array needs to be fixed before hand in FPGA vi;
Loop rates limited by longest path.If the process takes longer than the defined loop timer, it will use the longer one.

Attached is my code. In the producer loop, we generate a train of pulses and push them into a FIFO; in the consumer loop, we pop the data and output it on Connector1/Port0.

I’m somehow preventimg myself from updating the posts too frequently. It’s always harder to write the 10th post (or post after 1 month). I hope I can stick on this.

Related Posts: Study note of LabVIEW FPGA (1)                           Study note of LabVIEW FPGA (3) — Multi-line transmission

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12 comments on “Study note of LabVIEW FPGA (2)

  1. Otis says:

    You can actually speed up your FPGA compile time by changing some of your options within the project.

    1. Right-click on the FPGA Target within your LabVIEW Project
    2. Select Xilinx Options
    3. Uncheck “Use recommended settings”
    4. Select Design Strategy > Minimum Compilation Time

    For your final deployed project, I would still recommend using the recommended settings; however, if you’re just building a quick application on the FPGA and want to get it up and running more quickly this can shave a lot of time off your compile process.

    • foolooo says:

      Thanks Otis! It’s always pleasure hearing from some one! I’m trying that and I’ll post my comparision asap.
      It’s annouying that I have to ‘approve’ any comment manually. I’ll try if I can set the default action as ‘Approve’.

    • foolooo says:

      Hi Otis, refer to your suggestion I compared the compling results. Unfortunately, the progress is not obvious.
      I just tried the vi I posted. It took 16’4″ under recommended setting, and 15’50” under minimum compliation time. I think it would differ with different vi.
      I’ll keep trying later and will let you know if it goes faster.

      • Otis says:

        I guess I should have started with, “Results May Vary.” I’ve had improvements on some of my VIs where it went from 9 min compiles to 4 min compiles, so it can give you a significant in some cases.

        Ultimately though, the compiling is at the mercy of the Xilinx Compiler’s timing. And there’s only certain things you can do to increase your compile times. Some things like making sure to not put arrays on your front panel are pretty obvious; however, even if you do everything perfectly you could have to wait awhile. The only real way to guarantee faster compile times is to throw more power at it in the manner of more CPUs or more RAM. Many companies that compile lots of FPGA VIs will have a dedicated compile server that’s got awesome specs.

        For the rest of us we just do this:
        http://xkcd.com/303/

    • foolooo says:

      Otis, the link is awsome!:D
      Ye, you are right. I’ll remove the array from the front panel. And in the future, if I need to transfer arrays, I think I’ll use “single number+for loop” instead. Thanks a lot!

      Btw, it seems that I cannot reply your reply reply…

    • foolooo says:

      Thanks for your suggestions. Since I want to handle the array in a stict period, so I think doing it on FPGA is the choice. The array is small now but for the future work I want it to be scable. I’m reading your links now, and will give it a shot tomorrow.

      Cheers. 🙂

  2. Otis says:

    Edit: 1. Right-click on the FPGA Target within your LabVIEW Project, and select Properties.

  3. Todd says:

    Hey foolooo! I just found this blog and wanted to say thanks for all the great content and discussion. Shoot me an email if you ever run into any roadblocks or have a bad experience…I can help point you in the right direction. Also (you probably already know this), but check out the NI Disucssion Forums (http://forums.ni.com) and the NI Community (http://www.ni.com/community) for support material and networking.

    Happy wire-working!

    Todd

    • foolooo says:

      Hi Todd, thank you for your help in advance. Yes, I am a member of NI forum and community and I find it very useful. For now I’m just playing with the R series card. Coming up with problems, recording them and resolving them are a fun to me:) I’ll let your know if I cannot fix the problems. Cheers.

      Best wishes,
      Bo

  4. […] Post: Study note of LabVIEW FPGA (2) , Study note of LabVIEW FPGA (3) — […]

  5. […] Related Posts: Study note of LabVIEW FPGA (1)                           Study note of LabVIEW FPGA (2) […]

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